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[導(dǎo)讀]實(shí)際上,每個(gè)產(chǎn)品設(shè)計(jì)必須經(jīng)歷數(shù)字提取和真實(shí)模擬世界。設(shè)計(jì)前期的一些考慮將焦點(diǎn)放在接口設(shè)計(jì)上。 20世紀(jì)后半葉的技術(shù)創(chuàng)新達(dá)到空前的速度。不像以前,這個(gè)時(shí)期的許多進(jìn)

實(shí)際上,每個(gè)產(chǎn)品設(shè)計(jì)必須經(jīng)歷數(shù)字提取和真實(shí)模擬世界。設(shè)計(jì)前期的一些考慮將焦點(diǎn)放在接口設(shè)計(jì)上。

20世紀(jì)后半葉的技術(shù)創(chuàng)新達(dá)到空前的速度。不像以前,這個(gè)時(shí)期的許多進(jìn)步很快應(yīng)用到廣泛的消費(fèi)市場(chǎng)。直到那個(gè)時(shí)候,因?yàn)槲覀兊纳鐣?huì)趨向于從消費(fèi)者利益中榨取全部?jī)r(jià)值和壽命,商人需要對(duì)新產(chǎn)品產(chǎn)生足夠興趣,引起顧客轉(zhuǎn)變進(jìn)一步需要:這是可任意使用經(jīng)濟(jì)的起源。

19世紀(jì)50年代開(kāi)始,廣告使用例如“噴氣時(shí)代”、“原子時(shí)代”和“空間時(shí)代”的習(xí)語(yǔ),將產(chǎn)品連接到顯現(xiàn)和快速
改變現(xiàn)代性的社會(huì)映像。諷刺地,這些習(xí)語(yǔ)也許都沒(méi)有剩下的一個(gè)有力量:“數(shù)字時(shí)代”。19世紀(jì)70年代開(kāi)始,時(shí)代恰好表明關(guān)聯(lián)事物不是簡(jiǎn)單的現(xiàn)代,而與早期產(chǎn)品有明顯不同。

確實(shí),數(shù)字提取改革了我們的工業(yè)、幾乎每個(gè)經(jīng)濟(jì)部門(mén)和所有生活的方面。雖然結(jié)果相當(dāng)真實(shí),但這個(gè)提取嚴(yán)格的說(shuō)只是概念上的。結(jié)果,事實(shí)上每個(gè)產(chǎn)品設(shè)計(jì)必須從數(shù)字抽取橋接到真實(shí)模擬世界。

需求的東西明顯瑣碎:IC布局考慮、IC和PCB之間接口、PCB的布版、到箱子遠(yuǎn)處點(diǎn)的產(chǎn)品接口、系統(tǒng)箱和系統(tǒng)網(wǎng)絡(luò),所有都必須處理本質(zhì)相似的接口關(guān)系。不管這些條目,這個(gè)檢查保持了非常不同的范圍,跨越了多于10階的量級(jí)。事實(shí)是,雖然接口挑戰(zhàn)了帶寬的增長(zhǎng),問(wèn)題卻通過(guò)頻譜出現(xiàn)了。

早期設(shè)計(jì)階段的一些考慮著眼于接口設(shè)計(jì)。接口瑣碎特性的結(jié)果是在產(chǎn)品定義階段就開(kāi)始詳述接口需求,在結(jié)構(gòu)圖、原理圖和仿真階段改進(jìn)。

我區(qū)別反復(fù)設(shè)計(jì)改進(jìn)的過(guò)程——有目的地改進(jìn)設(shè)計(jì)過(guò)程和反復(fù)設(shè)計(jì)一系列修改。產(chǎn)品定義階段的第一個(gè)關(guān)口應(yīng)該建立對(duì)接口價(jià)格、復(fù)雜性和設(shè)計(jì)時(shí)間的粗略估計(jì)。第一階段的輸出在圖表階段作為執(zhí)行定型的檢查。從前兩個(gè)階段,不同價(jià)格或復(fù)雜性估計(jì)作為對(duì)三個(gè)條件中一個(gè)的警告:

接口設(shè)計(jì)影響加工。

第一階段未能合理計(jì)算所有產(chǎn)品定義需求。

改變產(chǎn)品定義浪費(fèi)了費(fèi)用和復(fù)雜性估計(jì),這些估計(jì)需要更新工程管理行為的部分。

在后來(lái)的設(shè)計(jì)階段,做相似的檢查。

作為階段一的起始點(diǎn),記住每個(gè)接口的信號(hào)源、線和客戶(hù)端的特性。不管信號(hào)的“數(shù)字”意義,記住接口動(dòng)作是模擬和多參數(shù)的??紤]每條線帶寬的需求,源阻抗、信號(hào)幅值和運(yùn)行長(zhǎng)度;連接媒介的特征;噪聲源或干擾的存在,所有前后接收端電路信號(hào)的保真需求。在仿真階段,比較最壞情況下發(fā)送和接收端波形??紤]前后信號(hào)調(diào)理技術(shù),改進(jìn)不足。如果延遲這些檢查到原型估價(jià),也許將改進(jìn)設(shè)計(jì)滑到反復(fù)設(shè)計(jì),需要更多花費(fèi)。

英文原文:

Building bridges: Specifying and refining inteRFace designs

Virtually every product design must bridge the digital abstraction and the real analog world. A few considerations early in the design phase can focus an interface design.

By Joshua Israelsohn, Contributing Technical Editor -- EDN, 11/8/2007

Technological innovation during the second half of the 20th century came at an unprecedented pace, and, unlike earlier times, many advances during this interval moved rapidly into the broad consumer market. Because our society, until that time, tended to wring the full value and lifetime from a consumer good, marketers needed to generate sufficient excitement for new products to cause customers to switch in advance of necessity: the origin of the disposable economy.

Starting in the 1950s, advertising copy used phrases such as “jet age,” “atomic age,” and “Space Age” to connect products to a societal image of emerging and rapidly changing modernity. Ironically, perhaps, none of these phrases had much staying power save one: the “digital age,” which, beginning in the 1970s, correctly suggested that associated goods weren't simply modern but were manifestly different from products of earlier times.

Indeed, the digital abstraction has revolutionized our industry, almost every sector of our economy, and all but a few aspects of our lives. Though the effects have been quite real, this abstraction is, as all are, strictly conceptual. As a
result, virtually every product design must bridge the digital abstraction and the real analog world.

This requirement is remarkably fractal-like: Layout considerations within an IC, the inteRFace between an IC and its PCB, the PCB's layout, the product interface to points beyond the box, systems of boxes, and networks of systems all must contend with essentially similar interface concerns. This observation holds despite these items' enormously different scales, which can span more than 10 orders of magnitude. It is also the case that, though interface challenges grow with bandwidth, the issue arises throughout the spectrum.

A few considerations early in the design phase can focus an interface design. A consequence of the fractal-like traits of interfaces is that you can begin specifying interface requirements at the product-definition phase and refine them at the block-diagram, schematic, and simulation phases.

I distinguish this process of design refinement from iterative design—design refinement being a purposeful process of design in phases, and iterative design being a sequence of design repairs. The first pass at the product-definition phase should allow you to establish a good rough estimate for an interface's cost, complexity, and design time. The first phase's output can serve as your check as an implementation takes shape at the block-diagram phase. Disparities in cost or complexity estimates from the first and second phases serve as warnings against one of three conditions:

The interface design is heading off into the toolies.

The first phase failed to account properly for all product-definition requirements.

Changes to the product definition have made obsolete the cost and complexity estimates, and these estimates require updating as part of your project-management activities.

Make similar checks at subsequent design phases.

As a phase-one starting point, bear in mind the signal-source, -line, and -client attributes for each interface. Despite your signal's “digital” significance, remember that interface behaviors are analog and multiparametric. Take into account each line's bandwidth requirement, source impedance, signal magnitude, and run length; the characteristics of the connecting media; and the presence of noise sources or interferers, all in the context of the receiver-side circuit's signal-fidelity requirements. In the simulation phase, compare the transmitter- and receiver-side waveforms under the worst-case combination of these measures. Consider pre- and post-signal-conditioning techniques to correct deficiencies. If you delay these observations until prototype evaluation, you may slip from design refinement into a more costly course of iterative design.

英文原文地址:http://www.edn.com/article/CA6495304.html

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