ST公司重定位向量表的庫函數(shù)：

void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)

{

assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));

assert_param(IS_NVIC_OFFSET(Offset));

SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);

}

其中NVIC_VectTab要么是FLASH要么是RAM的起始位置，Offset: Vector Table base offset field. This value must be a multiple of 0x200，這里先是IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)斷言機制，ST公司技術(shù)支持給我的回信是這么說的“The max flash size is 1MB, that is 0x100000, so the vector table must be placed within this address range, so ((OFFSET) < 0x000FFFFF) is checked.”f10x 內(nèi)置flash最大也就512K，SRAM內(nèi)置是64k，并沒有看到官方人員說的1MB，我想這些斷言機制恐怕也是為了給很多芯片共同使用而寫的，也就是說實際還是要自己小心著用啊~

然后(Offset & (uint32_t)0x1FFFFF80)事實上就是取了Offset的[28：7]位。但是你還是需要人為讓其為0x200的倍數(shù)，至于為什么，

在ARM官方給出的Cortex-m3 technial reference manul中是這么說的：

The Vector Table Offset Register positions the vector table in CODE or SRAM space.

The default, on reset, is 0 (CODE space). When setting a position, the offset must be

aligned based on the number of exceptions in the table. This means that theminimal

alignment is 32 words that you can use for up to 16 interrupts. For more interrupts, you

must adjust the alignment by rounding up to the next power of two. For example, if you

require 21 interrupts, the alignment must be on a 64-word boundary because table size

is 37 words, next power of two is 64.

所以由于人家規(guī)定要對齊向量表，由于stm32的中斷向量一共有68+16=84個，應(yīng)該把這個數(shù)增加到下一個2的整數(shù)倍即128，然后換算成地址范圍128*4=512，就得到了0x200。